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1 ltc1430a high power step-down switching regulator controller s f ea t u re d u escriptio the ltc ? 1430a is a high power, high efficiency switching regulator controller optimized for 5v to 1.xv-3.xv applica- tions. it includes a precision internal reference and an inter- nal feedback system that can provide output regulation of 1% over temperature, load current and line voltage shifts. the ltc1430a uses a synchronous switching architecture with two n-channel output devices, eliminating the need for a high power, high cost p-channel device. additionally, it senses output current across the drain-source resistance of the upper n-channel fet, providing an adjustable cur- rent limit without an external low value sense resistor. the ltc1430a includes a fixed frequency pwm oscillator for low output ripple under virtually all operating condi- tions. the 200khz free-running clock frequency can be externally adjusted from 100khz to above 500khz. the ltc1430as maximum duty cycle is typically 93.5% com- pared to 88% for the ltc1430. this permits 3.3v to 2.xv conversion using a low power 5v supply. the ltc1430a features low 350 m a quiescent current, allowing greater than 90% efficiency operation in converter designs from 1a to greater than 50a output current. shutdown mode drops the ltc1430a supply current to 1 m a. for new designs, refer to the ltc3830 . n high power 5v to 1.xv-3.xv switching controller: can exceed 10a output n maximum duty cycle > 90% permits 3.3v to 2.xv conversion using a low power 5v supply n all n-channel external mosfets n fixed frequency operationsmall l n excellent output regulation: 1% over line, load and temperature variations n high efficiency: over 95% possible n no low value sense resistor needed n outputs can drive external fets with up to 10,000pf gate capacitance n quiescent current: 350 m a typ, 1 m a in shutdown n fast transient response n adjustable or fixed 3.3v output n available in 8-lead so and 16-lead gn and so packages u a o pp l ic at i ty p i ca l efficiency typical 5v to 3.3v, 10a application + c in 220 m f 4 c out 330 m f 6 + + + 2.7 m h/15a pv cc1 v cc freqset shdn comp ss pv cc2 pgnd gnd g1 i fb i max g2 nc 1430 ta01 shutdown fb nc q1a, q1b, q2: motorola mtd20n03hl c in : avx-tpse227m010r0100 c out : avx-tpse337m006r0100 sense + ltc1430a sense 16k 100 w r c 7.5k c c 4700pf c1 220pf mbr0530t1 1k 0.1 m f 1 m f 0.01 m f 0.1 m f 4.7 m f 0.1 m f 3.3v 10a q1a, q1b 2 in parallel q2 5v load current (a) 40 70 100 90 80 50 60 efficiency (%) 10 1430 ta02 0.1 1 t a = 25 c pv cc = 5v v out = 3.3v , ltc and lt are registered trademarks of linear technology corporation. pentium is a registered trademark of intel corporation. amd-k6 is a registered trademark of advanced micro devices, inc. u s a o pp l ic at i n power supply for pentium ? ii and amd-k6 ? microprocessors n high power 5v to 3.xv regulators n local regulation for dual voltage logic boards n low voltage, high current battery regulation
2 ltc1430a a u g w a w u w a r b s o lu t exi t i s supply voltage v cc ....................................................................... 9v pv cc1, 2 .............................................................. 13v input voltage i fb ......................................................... C 0.3v to 18v all other inputs ...................... C 0.3v to (v cc + 0.3v) junction temperature ........................................... 150 c operating temperature range ltc1430ac ............................................. 0 c to 70 c ltc1430ai ........................................ C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c wu u package / o rder i for atio order part number 1 2 3 4 5 6 7 8 top view s package 16-lead plastic so gn package 16-lead plastic ssop 16 15 14 13 12 11 10 9 g1 pv cc1 pgnd gnd sense fb sense + shdn g2 pv cc2 v cc i fb i max freqset comp ss t jmax = 150 c, q ja = 130 c/w (gn) t jmax = 150 c, q ja = 110 c/w (s) 1 2 3 4 8 7 6 5 top view g1 pv cc1 gnd fb g2 v cc /pv cc2 comp shdn s8 package 8-lead plastic so t jmax = 150 c, q ja = 150 c/w s8 part marking 1430a ltc1430acs8 ltc1430acgn ltc1430aign ltc1430acs order part number consult factory for military grade parts. electrical characteristics ltc1430ac ltc1430ai symbol parameter conditions min typ max min typ max units v cc supply voltage l 484 8v pv cc pv cc1 , pv cc2 voltage l 3133 13v v out output voltage figure 1 3.30 3.30 v v fb feedback voltage sense + and sense C floating , l 1.25 1.265 1.28 1.23 1.265 1.29 v v comp = 2.5v d v out output load regulation figure 1, i out = 0a to 10a 5 5 mv output line regulation figure 1, v cc = 4.75v to 5.25v 1 1 mv i vcc supply current (v cc only) figure 2, v shdn = v cc l 350 700 350 700 m a v shdn = 0v 1 10 1 10 m a i pvcc supply current (pv cc ) figure 2, pv cc = 5v, v shdn = v cc (note 3) 1.5 1.5 ma v shdn = 0v 0.1 0.1 m a f osc internal oscillator frequency freqset floating l 140 200 260 130 200 300 khz v cc = 5v, t a = 25 c (note 2) unless otherwise noted. (note 1)
3 ltc1430a v cc = 5v, t a = 25 c (note 2) unless otherwise noted. electrical characteristics ltc1430ac ltc1430ai symbol parameter conditions min typ max min typ max units v ih shdn input high voltage l 2.4 2.4 v v il shdn input low voltage l 0.8 0.8 v i in shdn input current l 0.1 1 0.1 1 m a g mv error amplifier transconductance l 350 650 1100 300 650 1200 m mho g mi i lim amplifier transconductance (note 4) 2400 2400 m mho a v error amplifier open-loop gain (note 5) l 40 48 40 48 db i max i max sink current v i(max) = v cc l 8 12 16 8 12 17 m a i ss soft start source current v ss = 0v l C8 C12 C16 C8 C12 C17 m a t r , t s driver rise/fall time figure 3, pv cc1 = pv cc2 = 5v 80 250 80 250 ns t nov driver non-overlap time figure 3, pv cc1 = pv cc2 = 5v 25 130 250 25 130 250 ns dc max maximum duty cycle figure 3, v comp = v cc , l 90 93.5 89 93.5 % v fb = 1.265v the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 3: supply current in normal operation is dominated by the current needed to charge and discharge the external fet gates. this will vary with the ltc1430a operating frequency, operating voltage and the external fets used. note 4: the i lim amplifier can sink but cannot source current. under normal (not current limited) operation, the i lim output current will be zero. note 5: the open-loop dc gain and transconductance from the fb pin (sense + and sense C floating) to comp pin will be a v and gm v respectively.
4 ltc1430a temperature ( c) ?0 12.5 13.0 14.0 20 60 1430 g01 12.0 11.5 ?0 0 40 80 100 11.0 10.5 13.5 i max current ( m a) v cc = 5v temperature ( c) ?0 70 duty cycle (%) 75 85 90 95 0 40 60 1430 g03 80 ?0 20 80 100 100 v comp = v cc v fb = 1.265v temperature ( c) ?0 210 220 240 20 60 1430 g02 200 190 ?0 0 40 80 100 180 170 230 oscillator frequency (khz) v cc = 5v freqset floating maximum duty cycle vs temperature oscillator frequency vs temperature error amplifier transconductance vs temperature temperature ( c) ?0 350 transconductance ( m mho) 400 500 550 600 850 700 0 40 60 100 1430 g04 450 750 800 650 ?0 20 80 g m = d i comp d v fb d v fb vs temperature temperature ( c) ?0 d v fb (mv) 6 8 20 1430 g05 0 ? ? ?0 0 40 ? ?0 10 4 2 ? 60 80 100 v cc = 5v load regulation load current (a) 0 1.0 d v out (mv) 0.8 0.4 0.2 0 0.4 1 5 7 1460 g06 0.6 0.2 4 9 10 2 3 68 t a = 25 c v out = 3.3v v cc = 5v figure 4 supply current vs oscillator frequency oscillator frequency (khz) 1 supply current (ma) 10 100 1000 0 200 300 400 0.1 100 500 1430 g08 ipv cc (loaded with 10,000pf, pv cc = 12v) ipv cc (no load, pv cc = 5v) ipv cc (no load, pv cc = 12v) iv cc t a = 25 c v cc = 5v figure 4 output voltage vs load current with current limit load current (a) 0 output voltage (v) 1.5 2.0 2.5 6 10 1430 g07 1.0 0.5 0 24 8 3.0 3.5 4.0 12 t a = 25 c v cc = 5v figure 4 r i(max) = 10k r i(max) = 16k typical perfor a ce characteristics uw i max pin sink current vs temperature
5 ltc1430a comp (pin 10/pin 6): external compensation. the comp pin is connected directly to the output of the error amplifier and the input of the pwm. an rc network is used at this node to compensate the feedback loop to provide opti- mum transient response. see applications information for compensation details. freqset (pin 11/na): frequency set. this pin is used to set the free running frequency of the internal oscillator. with the pin floating, the oscillator runs at about 200khz. a resistor from freqset to ground will speed up the oscillator; a resistor to v cc will slow it down. see applica- tions information for resistor selection details. i max (pin 12/na): current limit set. i max sets the thresh- old for the internal current limit comparator. if i fb drops below i max with g1 on, the ltc1430a will go into current limit. i max has a 12 m a pull-down to gnd. it can be adjusted with an external resistor to pv cc or an external voltage source. i fb (pin 13/na): current limit sense. connect to the switched node at the source of q1 and the drain of q2 through a 1k resistor. the 1k resistor is required to prevent voltage transients from damaging i fb . this pin can be taken up to 18v above gnd without damage. v cc (pin 14/pin 7): power supply. all low power internal circuits draw their supply from this pin. connect to a clean power supply, separate from the main pv cc supply at the drain of q1. this pin requires a 4.7 m f or greater bypass capacitor. 8-lead parts have v cc and pv cc2 tied together at pin 7 and require at least a 10 m f bypass to gnd. pv cc2 (pin 15/pin 7): power v cc for driver 2. this is the power supply input for g2. g2 will swing from gnd to pv cc2 . pv cc2 is usually connected to the main high power supply. 8-lead parts have v cc and pv cc2 tied together at pin 7 and require at least a 10 m f bypass to gnd. g2 (pin 16/pin 8): driver output 2. connect this pin to the gate of the lower n-channel mosfet, q2. this output will swing from pv cc2 to pgnd. it will always be low when g1 is high. pi fu ctio s uu u g1 (pin 1/pin 1): driver output 1. connect this pin to the gate of the upper n-channel mosfet, q1. this output will swing from pv cc1 to pgnd. it will always be low when g2 is high. pv cc1 (pin 2/pin 2): power v cc for driver 1. this is the power supply input for g1. g1 will swing from pgnd to pv cc1 . pv cc1 must be connected to a potential of at least pv cc + v gs(on) (q1). this potential can be generated using an external supply or a simple charge pump connected to the switching node between the upper mosfet and the lower mosfet; see applications information for details. pgnd (pin 3/pin 3): power ground. both drivers return to this pin. it should be connected to a low impedance ground in close proximity to the source of q2. 8-lead parts have pgnd and gnd tied together at pin 3. gnd (pin 4/pin 3): signal ground. all low power internal circuitry returns to this pin. to minimize regulation errors due to ground currents, gnd should be connected to pgnd right at the ltc1430a. 8-lead parts have pgnd and gnd tied together internally at pin 3. sense C , fb, sense + (pins 5, 6, 7/pin 4): these three pins connect to the internal resistor divider and to the internal feedback node. to use the internal divider to set the output voltage to 3.3v, connect sense + to the positive terminal of the output capacitor and sense C to gnd. fb should be left floating in applications that use the internal divider. to use an external resistor divider to set the output voltage, float sense + and sense C and connect the exter- nal resistor divider to fb. shdn (pin 8/pin 5): shutdown. a ttl compatible low level at shdn for longer than 50 m s puts the ltc1430a into shutdown mode. in shutdown, g1 and g2 go low, all internal circuits are disabled and the quiescent current drops to 10 m a max. a ttl compatible high level at shdn allows the part to operate normally. ss (pin 9/na): soft start. the ss pin allows an external capacitor to be connected to implement a soft start func- tion. an external capacitor from ss to ground controls the start-up time and also compensates the current limit loop, allowing the ltc1430a to enter and exit current limit cleanly. see applications information for more details. (16-lead package/8-lead package)
6 ltc1430a test circuits + + i lim fb min pwm max + 40mv 20k + 1.265v 12 m a + 40mv 12 m a 12.4k pv cc1 shdn freqset comp ss i max v cc pv cc2 g1 g2 pgnd i fb fb sense + sense 1430 bd internal shutdown 50 m s delay block diagra m w figure 1 + c in 220 m f 4 c out 330 m f 6 + + 1 m f + + 2.7 m h/15a pv cc1 v cc freqset shdn comp ss pv cc2 pv cc2 = 5v pv cc1 = 12v pgnd gnd g1 i fb i max g2 nc 1430 f01 shutdown fb nc sense + ltc1430a sense 1.61k 1k fb nc nc sense + sense ltc1430a fb measurement v out 100 w r c 7.5k c c 4700pf c1 220pf 1 m f 0.01 m f 0.1 m f 4.7 m f 3.3v q1a, q1b 2 in parallel q2 q1a, q1b, q2: motorola mtd20n03hl c in : avx-tpse227m010r0100 c out : avx-tpse337m006r0100
7 ltc1430a test circuits figure 4 shdn v shdn i max freqset comp ss nc nc nc nc v cc pv cc2 ltc1430a pv cc pv cc1 i fb gnd pgnd sense + sense 1430 f02 g1 g2 fb nc nc nc v cc figure 2 figure 3 ltc1430a pv cc1 5v v cc v comp v fb pv cc2 gnd pgnd g1 rise/fall g2 rise/fall g1 g2 comp fb 10,000pf 1430 f03 10,000pf 10 m f 0.1 m f + + c in 220 m f 4 c out 330 m f 6 + + + 2.7 m h/15a pv cc1 v cc freqset shdn comp ss pv cc2 v cc v in = 5v pgnd gnd g1 i fb i max g2 nc 1430 f04 shutdown fb nc sense + ltc1430a sense 100 w r c 7.5k c c 4700pf c1 220pf 1n4148 1 m f 0.01 m f 0.1 m f 4.7 m f 0.1 m f 0.1 m f 3.3v q1a, q1b 2 in parallel q2 1k 16k q1a, q1b, q2: motorola mtd20n03hl c in : avx-tpse227m010r0100 c out : avx-tpse337m006r0100
8 ltc1430a applicatio n s i n for m atio n wu u u overview t he ltc1430a is a voltage feedback pwm switching regulator controller (see block diagram) designed for use in high power, low voltage step-down (buck) converters. it includes an onboard pwm generator, a precision refer- ence trimmed to 0.5%, two high power mosfet gate drivers and all necessary feedback and control circuitry to form a complete switching regulator circuit. the pwm loop nominally runs at 200khz. the 16-lead versions of the ltc1430a include a current limit sensing circuit that uses the upper external power mosfet as a current sensing element, eliminating the need for an external sense resistor. also included in the 16-lead version is an internal soft start feature that requires only a single external capacitor to operate. in addition, 16-lead parts feature an adjustable oscillator which can run at frequencies from 50khz to 500khz, allowing added flexibility in external component selection. the 8-lead version does not include current limit, internal soft start or frequency adjustability. theory of operation primary feedback loop the ltc1430a senses the output voltage of the circuit at the output capacitor with the sense + and sense C pins and feeds this voltage back to the internal transconduc- tance amplifier fb. fb compares the resistor-divided out- put voltage to the internal 1.265v reference and outputs an error signal to the pwm comparator. this is then com- pared to a fixed frequency sawtooth waveform generated by the internal oscillator to generate a pulse width modu- lated signal. this pwm signal is fed back to the external mosfets through g1 and g2, closing the loop. loop compensation is achieved with an external compensation network at comp, the output node of the fb transconduc- tance amplifier. min, max feedback loops two additional comparators in the feedback loop provide high speed fault correction in situations where the fb amplifier may not respond quickly enough. min compares the feedback signal to a voltage 40mv (3%) below the internal reference. at this point, the min comparator overrides the fb amplifier and forces the loop to full duty cycle, set by the internal oscillator at about 93.5%. simi- larly, the max comparator monitors the output voltage at 3% above the internal reference and forces the output to 0% duty cycle when tripped. these two comparators prevent extreme output perturbations with fast output transients, while allowing the main feedback loop to be optimally compensated for stability. current limit loop the 16-lead ltc1430a devices include yet another feed- back loop to control operation in current limit. the current limit loop is disabled in the 8-lead device. the i lim ampli- fier monitors the voltage drop across external mosfet q1 with the i fb pin during the portion of the cycle when g1 is high. it compares this voltage to the voltage at the i max pin. as the peak current rises, the drop across q1 due to its r ds(on) increases. when i fb drops below i max , indicating that q1s drain current has exceeded the maximum level, i lim starts to pull current out of the external soft start capacitor, cutting the duty cycle and controlling the output current level. at the same time, the i lim comparator generates a signal to disable the min comparator to prevent it from conflicting with the current limit circuit. if the internal feedback node drops below about 0.8v, indi- cating a severe output overload, the circuitry will force the internal oscillator to slow down by a factor of as much as 100. if desired, the turn on time of the current limit loop can be controlled by adjusting the size of the soft start capacitor, allowing the ltc1430a to withstand short overcurrent conditions without limiting. by using the r ds(on) of q1 to measure the output current, the current limit circuit eliminates the sense resistor that would otherwise be required and minimizes the number of components in the external high current path. because power mosfet r ds(on) is not tightly controlled and varies with temperature, the ltc1430a current limit is not de- signed to be accurate; it is meant to prevent damage to the power supply circuitry during fault conditions. the actual current level where the limiting circuit begins to take effect may vary from unit to unit, depending on the power mosfets used. see soft start and current limit for more details on current limit operation.
9 ltc1430a applicatio n s i n for m atio n wu u u mosfet gate drive gate drive for the top n-channel mosfet q1 is supplied from pv cc1 . this supply must be above pv cc ( the main power supply input) by at least one power mosfet v gs(on) for efficient operation. an internal level shifter allows pv cc1 to operate at voltages above v cc and pv cc , up to 13v maximum. this higher voltage can be supplied with a separate supply, or it can be generated using a simple charge pump as shown in figure 5. when using a separate pv cc1 supply, the pv cc input may exhibit a large inrush current if pv cc1 is present during power up. the 93.5% maximum duty cycle ensures that the charge pump will always provide sufficient gate drive to q1. gate drive for the bottom mosfet q2 is provided through pv cc2 for 16-lead devices or v cc /pv cc2 for the 8-lead device. pv cc2 can usually be driven directly from pv cc with 16-lead parts, although it can also be charge pumped or connected to an alternate supply if desired. 3.3v input applications use 3.3v at pv cc and 5v at v cc and pv cc1 . see 3.3v input supply operation for more details. the 8-lead part requires an rc filter from pv cc to v cc to ensure proper operation; see input supply considerations. d z 12v 1n5242 optional use for pv cc 3 7v ltc1430a pv cc1 pv cc2 mbr0530t1 q1 l1 q2 g1 g2 pv cc c out v out 1430 f05 0.1 m f + figure 5. doubling charge pump q1 d1 v in v out controller 1430 f06a figure 6a. classical buck architecture q1 v in v out controller q2 1430 f06b figure 6b. synchronous buck architecture much lower than the v f of the diode in the classical circuit. this more than offsets the additional gate drive required by the second mosfet, allowing the ltc1430a to achieve efficiencies in the mid-90% range for a wide range of load currents. another feature of the synchronous architecture is that unlike a diode, q2 can conduct current in either direction. this allows the output of a typical ltc1430a circuit to sink current as well as sourcing it while remaining in regula- tion. the ability to sink current at the output allows the ltc1430a to be used with reactive or other nonconventional loads that may supply current to the regulator as well as drawing current from it. an example is a high current logic termination supply, such as the gtl terminator shown in the typical applications section. external component selection power mosfets two n-channel power mosfets are required for most ltc1430a circuits. these should be selected based pri- marily on threshold and on-resistance considerations; thermal dissipation is often a secondary concern in high efficiency designs. required mosfet threshold should be determined based on the available power supply voltages and/or the complexity of the gate drive charge pump synchronous operation the ltc1430a uses a synchronous switching architec- ture, with mosfet q2 taking the place of the diode in a classical buck circuit (figure 6). this improves efficiency by reducing the voltage drop and the resultant power dissipation across q2 to v on = (i)(r dson(q2) ), usually
10 ltc1430a u s a o pp l ic at i wu u i for atio the output load current. this current is always flowing through either q1 or q2 with the power dissipation split up according to the duty cycle: dc (q1) = v out v in dc (q2) = 1 v out v in = (v in ?v out ) v in the r on required for a given conduction loss can now be calculated by rearranging the relation p = i 2 r: r on (q1) = = p max (q1) dc(q1)(i max 2 ) v in (p max )(q1) v out (i max 2 ) r on (q2) = = p max (q2) dc(q2)(i max 2 ) v in (p max )(q2) (v in ?v out )(i max 2 ) p max should be calculated based primarily on required efficiency. a typical high efficiency circuit designed for 5v in, 3.3v at 10a out might require no more than 3% efficiency loss at full load for each mosfet. assuming roughly 90% efficiency at this current level, this gives a p max value of (3.3v)(10a/0.9)(0.03) = 1.1w per fet and a required r on of: r on (q1) = = 0.017 w (5v)(1.1w) (3.3v)(10a 2 ) r on (q2) = = 0.032 w (5v)(1.1w) (5v ?3.3v)(10a 2 ) note that the required r on for q2 is roughly twice that of q1 in this example. this application might specify a single 0.03 w device for q2 and parallel two more of the same devices to form q1. note also that while the required r on values suggest large mosfets, the dissipation numbers scheme. in 5v input designs where an auxiliary 12v supply is available to power pv cc1 and pv cc2 , standard mosfets with r ds(on) specified at v gs = 5v or 6v can be used with good results. the current drawn from this supply varies with the mosfets used and the ltc1430as operating frequency, but is generally less than 50ma. ltc1430a designs that use a doubler charge pump to generate gate drive for q1 and run from pv cc voltages below 7v cannot provide enough gate drive voltage to fully enhance standard power mosfets. when run from 5v, a doubler circuit may work with standard mosfets, but the mosfet r on may be quite high, raising the dissipation in the fets and costing efficiency. logic level fets are a better choice for 5v pv cc systems; they can be fully enhanced with a doubler charge pump and will operate at maximum efficiency. doubler designs running from pv cc voltages near 4v will begin to run into efficiency problems even with logic level fets; such designs should be built with tripler charge pumps (see figure 7) or with newer, super low threshold mosfets. note that doubler charge pump designs running from more than 7v and all tripler charge pump designs should include a zener clamp diode d z at pv cc1 to prevent transients from exceeding the absolute maximum rating at that pin. once the threshold voltage has been selected, r on should be chosen based on input and output voltage, allowable power dissipation and maximum required output current. in a typical ltc1430a buck converter circuit operating in continuous mode, the average inductor current is equal to d z 12v 1n5242 1n5817 1n5817 ltc1430a pv cc1 pv cc2 0.1 m f 10 m f q1 l1 q2 g1 g2 pv cc c out v out 1430 ?f07 0.1 m f 1n5817 + figure 7. tripling charge pump
11 ltc1430a u s a o pp l ic at i wu u i for atio are only 1.1w per device or less large to-220 packages and heat sinks are not necessarily required in high effi- ciency applications. siliconix si4410dy (in so-8) and motorola mtd20n03hl (in dpak) are two small, surface mount devices with r on values of 0.03 w or below with 5v of gate drive; both work well in ltc1430a circuits with up to 10a output current. a higher p max value will generally decrease mosfet cost and circuit efficiency and increase mosfet heat sink requirements. inductor the inductor is often the largest component in an ltc1430a design and should be chosen carefully. inductor value and type should be chosen based on output slew rate require- ments and expected peak current. inductor value is prima- rily controlled by the required current slew rate. the maximum rate of rise of the current in the inductor is set by its value, the input-to-output voltage differential and the maximum duty cycle of the ltc1430a. in a typical 5v to 3.3v application, the maximum rise time will be: 90% = (v in ?v out ) l amps second 1.53a m s i l where l is the inductor value in m h. a 2 m h inductor would have a 0.76a/ m s rise time in this application, resulting in a 6.5 m s delay in responding to a 5a load current step. during this 6.5 m s, the difference between the inductor current and the output current must be made up by the output capaci- tor, causing a temporary droop at the output. to minimize this effect, the inductor value should usually be in the 1 m h to 5 m h range for most typical 5v to 2.xv-3.xv ltc1430a circuits. different combinations of input and output volt- ages and expected loads may require different values. once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. peak current in the inductor will be equal to the maximum output load current added to half the peak- to- peak inductor ripple current. ripple current is set by the inductor value, the input and output voltage and the operating frequency. if the efficiency is high and can be approximately equal to 1, the ripple current is approxi- mately equal to: d i = dc (v in v out ) (f osc )(l) dc = v out v in f osc = ltc1430a oscillator frequency l = inductor value solving this equation with our typical 5v to 3.3v applica- tion, we get: = 2.8a p? (1.7)(0.66) (200khz)(2 m h) peak inductor current at 10a load: = 11.4a 10a + 2.8a 2 the inductor core must be adequate to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. note that the current may rise above this maximum level in circuits under current limit or under fault conditions in unlimited circuits; the inductor should be sized to withstand this additional current. input and output capacitors a typical ltc1430a design puts significant demands on both the input and output capacitors. under normal steady load operation, a buck converter like the ltc1430a draws square waves of current from the input supply at the switching frequency, with the peak value equal to the output current and the minimum value near zero. most of this current must come from the input bypass capacitor, since few raw supplies can provide the current slew rate to feed such a load directly. the resulting rms current flow in the input capacitor will heat it up, causing premature capacitor failure in extreme cases. maximum rms current occurs with 50% pwm duty cycle, giving an rms current value equal to i out /2. a low esr input capacitor with an adequate ripple current rating must be used to ensure reliable operation. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours (3 months) lifetime; further derating of the input capacitor ripple current beyond the manufacturers specification is recommended to extend the useful life of the circuit.
12 ltc1430a u s a o pp l ic at i wu u i for atio input supply considerations/charge pump the 16-lead ltc1430a requires four supply voltages to operate: pv cc for the main power input, pv cc1 and pv cc2 for mosfet gate drive and a clean, low ripple v cc for the ltc1430a internal circuitry (figure 8). in many applica- tions, pv cc and pv cc2 can be tied together and fed from a common high power supply, provided that the supply voltage is high enough to fully enhance the gate of external mosfet q2. this can be the 5v system supply if a logic level mosfet is used for q2. v cc can usually be filtered with an rc from this same high power supply; the low quiescent current (typically 350 m a) allows the use of relatively large filter resistors and correspondingly small filter capacitors. 100 w and 4.7 m f usually provide ad- equate filtering for v cc . the 8-lead version of the ltc1430a has the pv cc2 and v cc pins tied together inside the package (figure 9). this pin, brought out as v cc /pv cc2 , has the same low ripple re- quirements as the 16-lead part, but must also be able to supply the gate drive current to q2. this can be obtained the output capacitor in a buck converter sees much less ripple current under steady-state conditions than the input capacitor. peak-to-peak current is equal to that in the inductor, usually a fraction of the total load current. output capacitor duty places a premium not on power dissipation but on low esr. during an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the ltc1430a can adjust the inductor current to the new value. esr in the output capacitor results in a step in the output voltage equal to the esr value multiplied by the change in load current. a 5a load step with a 0.05 w esr output capacitor will result in a 250mv output voltage shift; this is a 7.6% output voltage shift for a 3.3v supply! because of the strong relationship between output capacitor esr and output load transient response, the output capacitor is usually chosen for esr, not for capacitance value; a capacitor with suitable esr will usually have a larger capacitance value than is needed to control steady-state output ripple. electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and esr can be used effectively in ltc1430a applications. os-con electrolytic capacitors from sanyo give excellent perfor- mance and have a very high performance/size ratio for an electrolytic capacitor. surface mount applications can use either electrolytic or dry tantalum capacitors. tantalum capacitors must be surge tested and specified for use in switching power supplies; low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. avx tps series surface mount devices are popular tantalum capaci- tors that work well in ltc1430a applications. a common way to lower esr and raise ripple current capability is to parallel several capacitors. a typical ltc1430a applica- tion might require an input capacitor with a 5a ripple current capacity and 2% output shift with a 10a output load step, which requires a 0.007 w output capacitor esr. sanyo os-con part number 10sa220m (220 m f/10v) capacitors feature 2.3a allowable ripple current at 85 c and 0.035 w esr; three in parallel at the input and six at the output will meet the above requirements. figure 9. 8-lead power supplies internal circuitry v cc /pv cc2 ltc1430a (8-lead) pv cc1 q1 l1 q2 g1 g2 pv cc c out v out 1430 f09 + figure 8. 16-lead power supplies internal circuitry v cc ltc1430a (16-lead) pv cc2 pv cc1 q1 l1 q2 g1 g2 pv cc c out v out 1430 f08 +
13 ltc1430a u s a o pp l ic at i wu u i for atio by using a larger rc filter from the pv cc pin; 22 w and 10 m f work well here. the 10 m f capacitor must be very close to the part (preferably right underneath the unit) or output regulation may suffer. for both versions of the ltc1430a, pv cc1 must be higher than pv cc by at least one external mosfet v gs(on) to fully enhance the gate of q1. this higher voltage can be provided with a separate supply (typically 12v) which should power up after pv cc , or it can be generated with a simple charge pump (figure 5). the charge pump consists of a schottky diode from pv cc to pv cc1 and a 0.1 m f capacitor from pv cc1 to the switching node at the drain of q2. this circuit provides 2pv cc C v f to pv cc1 while q1 is on and pv cc C v f while q1 is off where v f is the on voltage of the schottky diode. ringing at the drain of q2 can cause transients above 2pv cc at pv cc1 ; if pv cc is higher than 7v, a 12v zener diode should be included from pv cc1 to pgnd to prevent transients from damaging the circuitry at pv cc2 or the gate of q1. more complex charge pumps can be constructed with the 16-lead versions of the ltc1430a to provide additional voltages for use with standard threshold mosfets or very low pv cc voltages. a tripling charge pump (figure 7) can provide 2pv cc and 3pv cc voltages. these can be con- nected to pv cc2 and pv cc1 respectively, allowing stan- dard threshold mosfets to be used with 5v at pv cc or 5v logic level threshold mosfets to be used with 3.3v at pv cc . v cc can be driven from the same potential as pv cc2 , allowing the entire system to run from a single 3.3v supply. tripling charge pumps require the use of schottky diodes to minimize forward drop across the diodes at start-up. the tripling charge pump circuit will tend to rectify any ringing at the drain of q2 and can provide well more than 3pv cc at pv cc1 ; all tripling (or higher multiply- ing factor) circuits should include a 12v zener clamp diode d z to prevent overvoltage at pv cc1 . 3.3v input supply operation the ltc1430a can be used with input supply voltages lower than 5v as long as a low power 5v supply is available to power the ltc1430a itself and to provide gate drive to the external mosfets. a typical 3.3v to 2.5v application is shown in figure 10. the circuit can supply up to 10a at 2.5v output, and draws this power from the 3.3v supply. the 5v supply typically needs to supply about 20ma to provide gate drive to the external mosfets and keep the ltc1430a control circuits powered. for applications where there is no 5v supply available, see the ltc1649 data sheet. compensation and transient response the ltc1430a voltage feedback loop is compensated at the comp pin; this is the output node of the internal g m error amplifier. the loop can generally be compensated figure 10. 3.3v to 2.5v, 10a application + c in 220 m f 4 c out 330 m f 6 + + + 2.7 m h/15a pv cc1 v cc freqset shdn comp ss pv cc2 pgnd gnd g1 i fb i max g2 nc 1430 f10 shutdown fb nc nc q1a, q1b, q2: international rectifier irf7801 c in : avx-tpse227m010r0100 c out : avx-tpse337m006r0100 sense + ltc1430a sense 16k 100 w 976 w 1% 1k 1% r c 7.5k c c 4700pf c1 220pf mbr0530t1 1k 0.1 m f 1 m f 0.01 m f 0.1 m f 4.7 m f 1 m f 2.5v 10a q1a, q1b 2 in parallel q2 5v 3.3v
14 ltc1430a u s a o pp l ic at i wu u i for atio properly with an rc network from comp to gnd and an additional small c from comp to gnd (figure 11). loop stability is affected by inductor and output capacitor values and by other factors. optimum loop response can be obtained by using a network analyzer to find the loop poles and zeros; nearly as effective and a lot easier is to empirically tweak the r c values until the transient recovery looks right with an output load step. table 1 shows recommended compensation components for 5v to 3.3v applications based on the inductor and output capacitor values. the values were calculated using multiple paral- leled 330 m f avx tps series surface mount tantalum capacitors as the output capacitor. table 1. recommended compensation network for 5v to 3.3v application using multiple 330 m f avx output capacitors l1 ( m h) c out ( m f) r c (k w )c c ( m f) c1 (pf) 1 990 1.8 0.022 820 1 1980 3.6 0.01 470 1 4950 9.1 0.0047 150 1 9900 18 0.0022 82 2.7 990 3.6 0.01 470 2.7 1980 7.5 0.0047 220 2.7 4950 18 0.0022 82 2.7 9900 39 0.001 39 5.6 990 9.1 0.0047 150 5.6 1980 18 0.0022 82 5.6 4950 47 820pf 33 5.6 9900 91 470pf 15 10 990 18 0.0022 82 10 1980 39 0.001 39 10 4950 91 470pf 15 10 9900 180 220pf 10 output transient response is set by three major factors: the time constant of the inductor and the output capacitor, the esr of the output capacitor, and the loop compensation components. the first two factors usually have much more impact on overall transient recovery time than the third; unless the loop compensation is way off, more improvement can be had by optimizing the inductor and the output capacitor than by fiddling with the loop com- pensation components. in general, a smaller value induc- tor will improve transient response at the expense of ripple ltc1430a comp gnd sgnd 1430 f11 c1 c c r c figure 11. compensation pin hook-up and inductor core saturation rating. minimizing output capacitor esr will also help optimize output transient response. see input and output capacitors for more information. soft start and current limit the 16-lead versions of the ltc1430a include a soft start circuit at the ss pin; this circuit is used both for initial start- up and during current limit operation. the soft start and current limit circuitry is disabled in the 8-lead version. ss requires an external capacitor to gnd with the value determined by the required soft start time. an internal 12 m a current source is included to charge the external capacitor. soft start functions by clamping the maximum voltage that the comp pin can swing to, thereby control- ling the duty cycle (figure 12). the ltc1430a will begin to operate at low duty cycle as the ss pin rises to about 2v below v cc . as ss continues to rise, the duty cycle will increase until the error amplifier takes over and begins to regulate the output. when ss reaches 1v below v cc the 1430 f12 c ss comp ss ltc1430a 12 m a v cc fb figure 12. soft start clamps comp pin
15 ltc1430a u s a o pp l ic at i wu u i for atio longer overload conditions will allow the ss pin to reach a steady level, and the output will remain at a reduced voltage until the overload is removed. serious overloads will generate a larger overdrive at i lim , allowing it to pull ss down more quickly and preventing damage to the output components. the i lim amplifier output is disabled when q1 is off to prevent the low i fb voltage in this condition from activating the current limit. it is re-enabled a fixed 170ns after q1 turns on; this allows for the i fb node to slew back high and the i lim amplifier to settle to the correct value. as the ltc1430a goes deeper into current limit, it will reach a point where the q1 on-time needs to be cut to below 170ns to control the output current. this conflicts with the minimum settling time needed for proper operation of the i lim amplifier. at this point, a secondary current limit circuit begins to reduce the internal oscillator frequency, lengthening the off-time of q1 while the on-time remains constant at 170ns. this further reduces the duty cycle, allowing the ltc1430a to maintain control over the output current. under extreme output overloads or short circuits, the i lim amplifier will pull the ss pin more than 2v below v cc in a single switching cycle, cutting the duty cycle to zero. at this point all switching stops, the output current decays through q2 and the ltc1430a runs a partial soft start cycle and restarts. if the short is still present the cycle will repeat. peak currents can be quite high in this condition, but the average current is controlled and a properly designed circuit can withstand short circuits indefinitely with only moderate heat rise in the output fets. in addi- tion, the soft start cycle repeat frequency can drop into the low khz range, causing vibrations in the inductor which provide an audible alarm that something is wrong. oscillator frequency the ltc1430a includes an onboard current controlled oscillator which will typically free-run at 200khz. an internal 20 m a current is summed with any current in or out of the freqset pin (pin 11), setting the oscillator fre- quency to approximately 10khz/ m a. freqset is internally servoed to the ltc1430a reference voltage (1.265v). with freqset floating, the oscillator is biased from the ltc1430a will be in full operation. an internal switch shorts the ss pin to gnd during shutdown. the ltc1430a detects the output current by watching the voltage at i fb while q1 is on. the i lim amplifier compares this voltage to the voltage at i max (figure 13). in the on state, q1 has a known resistance; by calculating back- wards, the voltage generated at i fb by the maximum output current in q1 can be determined. as i fb falls below i max , i lim will begin to sink current from the soft start pin, causing the voltage at ss to fall. as ss falls, it will limit the output duty cycle, limiting the current at the output. eventually the system will reach equilibrium, where the pull-up current at the ss pin matches the pull-down current in the i lim amplifier; the ltc1430a will stay in this state until the overcurrent condition disappears. at this time i fb will rise, i lim will stop sinking current and the internal pull-up will recharge the soft start capacitor, restoring normal operation. note that the i fb pin requires an external 1k series resistor to prevent voltage transients at the drain of q2 from damaging internal structures. + i lim ltc1430a 1430 f13 r imax pv cc i max i fb ss c ss 12 m a q1 q2 12 m a v cc 1k 0.1 m f figure 13. current limit operation the i lim amplifier pulls current out of ss in proportion to the difference between i fb and i max . under mild overload conditions, the ss pin will fall gradually, creating a time delay before current limit takes effect. very short, mild overloads may not trip the current limit circuit at all.
16 ltc1430a u s a o pp l ic at i wu u i for atio be checked carefully in applications where operation near dropout is importantlike 3.3v to 2.5v converters. fre- quencies above 500khz can cause erratic current limit operation and are not recommended. layout considerations grounding proper grounding is critical for the ltc1430a to obtain specified output regulation. extremely high peak currents (as high as several amps) can flow between the bypass capacitors and the pv cc1 , pv cc2 and pgnd pins. these currents can generate significant voltage differences be- tween two points that are nominally both ground. as a general rule, gnd and pgnd should be totally separated on the layout, and should be brought together at only one point, right at the ltc1430a gnd and pgnd pins. this helps minimize internal ground disturbances in the ltc1430a by keeping pgnd and gnd at the same poten- tial, while preventing excessive current flow from disrupt- ing the operation of the circuits connected to gnd. the pgnd node should be as compact and low impedance as possible, with the negative terminals of the input and output capacitors, the source of q2, the ltc1430a pgnd node, the output return and the input supply return all clustered at one point. figure 14 is a modified schematic showing the common connections in a proper layout. note that at 10a current levels or above, current density in the pc board itself can become a concern; traces carrying high currents should be as wide as possible. output voltage sensing the 16-lead versions of the ltc1430a provide three pins for sensing the output voltage: sense + , sense C and fb. sense + and sense C connect to an internal resistor divider which is connected to fb. to set the output of the ltc1430a to 3.3v, connect sense + to the output as near to the load as practical and connect sense C to the common gnd/pgnd point. note that sense C is not a true differential input sense input; it is just the bottom of the internal divider string. connecting sense C to the ground near the load will not improve load regulation. for any other output voltage, the sense + and sense C pins should internal 20 m a source and runs at 200khz. connecting a 50k resistor from freqset to ground will sink an addi- tional 25 m a from freqset, causing the internal oscillator to run at approximately 450khz. sourcing an external 10 m a current into freqset will cut the internal frequency to 100khz. an internal clamp prevents the oscillator from running slower than about 50khz. tying freqset to v cc will cause it to run at this minimum speed. shutdown the ltc1430a includes a low power shutdown mode, controlled by the logic at the shdn pin. a high at shdn allows the part to operate normally. a low level at shdn stops all internal switching, pulls comp and ss to ground internally and turns q1 and q2 off. in shutdown, the ltc1430a itself will drop below 1 m a quiescent current typically, although off-state leakage in the external mosfets may cause the total pv cc current to be some- what higher, especially at elevated temperatures. when shdn rises again, the ltc1430a will rerun a soft start cycle and resume normal operation. holding the ltc1430a in shutdown during pv cc power up removes any pv cc1 sequencing constraints. external clock synchronization the ltc1430a shdn pin can double as an external clock input for applications that require a synchronized clock or a faster switching speed. the shdn pin terminates the internal sawtooth wave and resets the oscillator immedi- ately when it goes low, but waits 50 m s before shutting down the rest of the internal circuitry. a clock signal applied directly to the shdn pin will force the ltc1430a internal oscillator to lock to its frequency as long as the external clock runs faster than the internal oscillator frequency. the ltc1430a can be synchronized to fre- quencies between 250khz and 350khz with no additional components. the ltc1430a is synchronizable at frequencies from 200khz to 500khz. frequencies above 300khz can cause a decrease in the maximum obtainable duty cycle as rise/ fall time and propagation delay take up a large fraction of the switch cycle. circuits using these frequencies should
17 ltc1430a u s a o pp l ic at i wu u i for atio figure 14. typical schematic showing layout considerations figure 15. using external resistors to set output voltages ltc1430a v out sense + fb r1 nc nc r2 sense 1430 f15 be floated and an external resistor string should be con- nected to fb (figure 15). as before, connect the top resistor (r1) to the output as close to the load as practical and connect the bottom resistor (r2) to the common gnd/pgnd point. in both cases, connecting the top of the resistor divider (either sense + or r1) close to the load can significantly improve load regulation by compensating for any drops in pc traces or hookup wires between the ltc1430a and the load. power component hook-up/heat sinking as current levels rise much above 1a, the power compo- nents supporting the ltc1430a start to become physi- cally large (relative to the ltc1430a, at least) and can require special mounting considerations. input and output capacitors need to carry high peak currents and must have low esr; this mandates that the leads be clipped as short as possible and pc traces be kept wide and short. the power inductor will generally be the most massive single component on the board; it can require a mechanical hold- down in addition to the solder on its leads, especially if it is a surface mount type. the power mosfets used require some care to ensure proper operation and reliability. depending on the current levels and required efficiency, the mosfets chosen may be as large as to-220s or as small as so-8s. high efficiency circuits may be able to avoid heat sinking the power devices, especially with to-220 type mosfets. as an example, a 90% efficient converter working at a steady 3.3v/10a output will dissipate only (33w/90%)10% = 3.7w. the power mosfets generally account for the majority of the power lost in the converter; even assuming that they consume 100% of the power used by the converter, thats only 3.7w spread over two or three devices. a typical so-8 mosfet with a r on suitable to provide 90% efficiency in this design can commonly dissipate 2w when soldered to an appropriately sized piece of copper trace on a pc board. slightly less efficient or higher output current designs can often get by with standing a to-220 mosfet straight up in an area with some airflow; such an arrangement can dissipate as much as 3w without a heat sink. designs which must work in high ambient temperatures or which will be routinely overloaded will generally fare best with a heat sink. + + 1430 f14 3.3v 2.7 m h/15a total 1980 m f (330 m f 6.3v 6) q1a* q2* pv cc1 i max freqset gnd pgnd shdn comp nc ss pv cc2 v cc pgnd gnd r c 7.5k 0.1 m f 1 m f 0.1 m f c c 4700pf c1 220pf c ss 0.01 m f 4.7 m f 35v 100 w g1 i fb g2 fb sense + nc nc ltc1430a sense gnd pgnd * motorola mtd20n03hl mbr0530t1 5v q1b* total 880 m f (220 m f 10v 4) +
18 ltc1430a u s a o pp l ic at i wu u i for atio figure 17 is a synchronous buck regulator designed to provide a low voltage, very high current output from a 5v or lower input voltage. the circuit uses two 8-pin ltc1430acs8s, operated 180 out of phase from each other. each half of the circuit is good for 15a of output current, giving 30a total. the lt ? 1006 amplifier forces the two half circuits to share the load current equally. this scheme trades a small amount of additional control circuit complexity for radical reductions in the volume (hence cost) of the capacitors and inductors required. advan- tages of this approach include very low input and output ripple voltages, higher ripple frequency and extremely fast transient response. by incorporating two regulators phased opposite one another, both the input ripple currents and the output ripple currents tend to cancel. this permits running much higher ripple currents in the output inductors than would be tolerable with a single channel. the overall output ripple current in a two phase design is approximately 1/2 of a single channels ripple current, allowing the inductor value of each channel to be 1/2 that of what a single channel system would require for equal output ripple. since energy storage varies as the square of inductor current, and directly as the inductance, each inductor stores only 1/8th the energy of a single inductor design. since there are two inductors, total energy storage, and therefore inductor volume, is 1/4th that of a single phase system. a similar analysis can be done for the input capacitor requirements. in fact, a two-phase regulator will actually require less input capacitance than a single channel design at 1/2 the load current. figure 16 shows how the ripple currents tend to cancel one another. another significant advantage of the two-phase topology is radically improved transient response. during a load transient, each of the two channels runs to maximum (or minimum) duty cycle. the two ripple current terms now end up reinforcing one another rather than canceling. the result is a very high di/dt, hence, very fast transient recoveries. once steady state conditions return, the ripple currents begin to cancel again, providing very low output ripple voltage. a + b channel a channel b 2 m s/div 1430a f16 the clocking of the two channels is accomplished by the cd4047, a low cost, cmos mulitvibrator with a built-in divide-by-two flip flop. the cd4047 oscillator is set to run at 600khz and the q and q outputs drive the ltc1430a shutdown pins. since the sync signals are derived from the clocks divide-by-two outputs, they are inherently 180 out of phase and at the desired 300khz clock fre- quency. q1, d1 and the two resistors connected to q1s base are used to disable the synchronization at turn-on to prevent start-up problems. as long as the input-output differential voltage is large enough to turn on q1, the sync circuit is disabled and both ltc1430as will free run at 200khz. once the output rises above ? 1.5v, the regula- tors are allowed to lock to the clock. one challenge with a voltage mode two-phase design is current sharing. unlike current mode control which offers inherent current sharing, voltage mode control virtually assures that one channel will try to hog a large percentage of the load current. the circuit gets around this problem with a current share amplifier. the lt1006 op amp com- pares the voltage across both sense resistors and adds or subtracts a small current into the lower ltc1430as feedback divider, forcing it to match the upper ltc1430as current. the two pcb trace resistors are intentionally chosen to have a very low value to minimize power losses. the lt1006 features 80 m v typical v os , ensuring reason- ably accurate current sharing. there are three problems associated with this current sharing approach that must be dealt with. the first is that figure 16. output inductor currents 5a/div, 30a out
19 ltc1430a figure 17. low voltage 30a power supply + pv cc1 g1 ltc1430acs8 fb gnd pv cc2 g2 shdn comp 2 r20 1 w r22 1 w r23 1 w q2 si4410dy q4 si4410dy (optional) q3 si4410dy q5 si4410dy r21 1 w r13 0.002 w trace r12 10k r24 39k r10 10 w charge pump (optional) 1 4 3 7 8 5 c13 180pf c1 1 m f c2 1 m f c30 0.022 m f c22 1 m f c25 1 m f c14 1500pf r14 10k r1 51 w r3 1k r4 1k r6 3.09k 1% cd4047 (power from 5v clock) 6 ? ast ast osc q q +t ret rcc cx rx rst 5 4 6 10 11 13 8 12 3 1 2 9 d4 bat54 c23 0.47 m f c5 1 m f c18 1000pf c19 6800pf c11 470 m f 6.3v + c3 22 m f 25v c6 100pf npo 5% + c21 47 m f 10v + c10 470 m f 6.3v + c32 470 m f 6.3v + c7 470 m f 6.3v q1 mmbt3906lt1 d1 baw56ct1 12v 5v 5v 5v d2 bat54 r5 9.76k 1% r17 10k 1% v in v in optional r28 1 w l2 0.8 m h sync1 i sense1 sync2 sync1 notes: 1. l1 and l2 are panasonic etqp1f0r8lb 2. all resistors 5% unless otherwise marked 3. input and output caps are kemet t510 series 4. trace resistors r11 and r13 are 0.1" wide by 0.675" long c28 0.1 m f + c37 3300pf c31 0.022 m f c38 3300pf c29 1 m f c26 22 m f 25v pv cc1 g1 ltc1430acs8 fb gnd pv cc2 g2 shdn comp 2 r19 1 w r26 1 w r27 1 w r7 51k current share amplifier r8 4.3k q6 si4410dy q8 si4410dy (optional) q7 si4410dy q9 si4410dy r25 1 w r11 0.002 w trace r16 10 w charge pump (optional) 1 4 3 7 8 5 c16 180pf c24 1 m f c15 1500pf r15 10k 6 2 7 4 8 1 6 3 c27 0.47 m f c4 1 m f c17 1000pf 1430 f17 c36 1 m f c20 6800pf c12 470 m f 6.3v + c9 470 m f 6.3v + c33 470 m f 6.3v + c8 470 m f 6.3v + c39 1500 m f 6.3v sanyo c40 1500 m f 6.3v sanyo 12v 5v d3 bat54 r2 9.76k 1% r18 10k 1% r29 1 w l1 0.8 m h i sense2 sync2 12v i sense1 i sense2 v out c35 1 m f c34 1 m f + + r9 4.3k r30 1k r32 10 w r31 1k + lt1006 ref r24 r17 r18 r7 r24 r17 r18 r7 2.5v 10k 10k 10k 51k 39k 10k 10k 51k 2.0v 20k 16.9k 16.9k 62k 43k 16.9k 16.9k 62k 3.3v na na na na 36k 6.04k 6.04k 36k v out substitution table v in 3.3v 5v u s a o pp l ic at i wu u i for atio
20 ltc1430a u s a o pp l ic at i wu u i for atio the sense resistors should be well matched. this is accomplished by using trace resistors that are laid out symmetrically. since they are formed of the same material and processed identically, they will inherently match very well. note that the absolute value of these resistors is not important; only the match between them is of concern. the second issue is related to the reference point for the two sense voltages. in order to avoid the need to use a true differential amplifier to measure input current, the circuit is configured such that the input side of these resistors must be at the exact same potential. if the layout is not configured this way, the current sharing accuracy will prove disappointing. with only 0.2 w sense resistors, a seemingly small error will produce a rather large current mismatch between channels. the last issue is related to having a very noisy sense voltage. the current waveshape at the input to a buck regulator is trapezoidal. therefore, the sense amplifier must integrate the two current measurements in order that the average input currents be compared. the two-stage rc filter on the sense amplifier provides an adequately clean signal for the share circuit to operate correctly. high speed is not required in the current sense loop. in balanced operation any offsets in the slave regulator are dialed out by the sense amplifier. if a sudden load change should occur, both regulators will respond immediately and in the right direction. if there are any gain differences in the two loops there will need to be a small correction in the current share error voltage. this can occur over a relatively long time period with no adverse effects. as such, the share amplifiers bandwidth is on the order of a few hundred hz, ensuring good noise immunity. figure 18 demonstrates the high efficiency achieved with this two-phase converter. an efficiency > 90% is realized from a few amperes up to 30a. in theory and in practice, this multiphase approach can be extended to even higher current and output power levels. consult linear technol- ogy for further details. figure 18. low voltage 30a power supply efficiency load current (a) 0 50 efficiency (%) 60 70 80 5 10 15 20 1430 f18 25 90 100 55 65 75 85 95 30
21 ltc1430a dimensions in inches (millimeters) unless otherwise noted. u package d e sc r i pti o gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 0398 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.025 (0.635) bsc 0.009 (0.229) ref
22 ltc1430a u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
23 ltc1430a u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 s16 0695 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
24 ltc1430a ? linear technology corporation 1998 1430af, sn1430afs lt/tp 0898 4k ? printed in usa + + + + + + + l1 2.7 m h v cc i max shdn comp ss sgnd fset pv cc2 1 16 3 5 7 6 13 2 14 12 8 10 9 4 11 15 g1 g2 pgnd sense +sense fb i fb pv cc1 ltc1430a r6 10k r2 3 w r1 1k r3 3 w r4 51 r5 16.5k 1% r9 88.7k 1% r7 15k r10 3.3k r8 130k c7 0.1 m f c8 22 m f 35v c12 330 6.3v oscon c13 330 6.3v oscon c4 330 6.3v oscon 1.5v out c5 330 6.3v oscon shdn 5v c6 0.01 m f c16 0.1 m f c2 680pf c10 1 m f c11 0.068 m f c3 220pf c1 0.1 m f q1 si4410 q2 si4410 d2 mbrs340t3 d1 mbrs340t3 1430 ta03 330 6.3v tant 330 6.3v tant additional decoupling at the load d1 mbr0530t1 gtl terminator u a o pp l ic at i ty p i ca l related parts part number description comments ltc1142 current mode dual step-down switching regulator controller dual version of ltc1148 ltc1148 current mode step-down switching regulator controller synchronous, v in 20v ltc1149 current mode step-down switching regulator controller synchronous, v in 48v, for standard threshold fets ltc1159 current mode step-down switching regulator controller synchronous, v in 40v, for logic threshold fets ltc1266 current mode step-up/down switching regulator controller synchronous n- or p-channel fets, comparator/ low-battery detector ltc1267 current mode dual step-down switching regulator controller dual version of ltc1159 ltc1649 3.3v input synchronous switching regulator controller 3.3v input linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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